1. Field of the Invention
The present invention relates to integrated circuit testing and, more particularly, to functional testing of integrated circuit chips.
2. Description of the Related Art
The design of electrical circuits usually begins with computers modeling the functioning that electronic circuitry to be designed is to implement. The functional model is then typically simulated on a computer using a simulation program. Typically, the modeling programs and the simulation programs together form a Computer Aided Design (CAD) environment used by designers of electronic circuitry. Verilog Hardware Descriptive Language (Verilog HDL) is an example of a design description language that supports simulation at various levels of chip design.
The electronic circuitry is usually designed for an electronic circuit board (i.e., printed circuit board) and such boards frequently include numerous integrated circuit chips, wires or metal traces, passive devices, and active devices. FIG. 1 illustrates a simplified electronic circuit board 100 including various integrated circuit chips and other devices and components. In particular, the electronic circuit board 100 includes integrated circuit chip A 102, integrated circuit chip B 104, integrated circuit chip C 106, and miscellaneous other devices or components 108. The simplified electronic circuit board 100 also illustrates various wires or metal traces interconnecting the various chips, devices and components.
By using the modeling and simulation software packages, today""s electronic circuit designer is able to model the circuit board 100 without using hardware and to simulate the operation of the circuit board 100 again without using hardware. Hence, the simulation programs enable the designer to verify the functionality of the model that has been designed by simulating its operations in accordance with the model. Such simulations are carried out using functional tests which are deterministic stimuli designed to produce a desired response in the design. The simulated response of the design can then be compared to an expected response to determine whether or not the model of the circuit board 100 is functioning correctly. If the model of the circuit board 100 is not functioning correctly, the model is modified. Thereafter, the circuit board 100 is again simulated. The process is repeated until the model of the circuit board 100 functions correctly. In verifying the functionality of the model of the circuit board 100, numerous functional tests are performed and their responses obtained.
Once the design has been verified by the board level simulation, the individual devices associated with the circuit board 100 are manufactured. It is not uncommon for the manufacturer of the isolated devices to be different vendors. Such vendors are required to test the devices they produce for use in the circuit board 100. As an example, the devices include integrated circuit chips such as Application Specific Integrated Circuits (ASICs). Normally, vendors of integrated circuit chips perform structural tests so as to primarily verify their fabrication process (e.g., test for defects). In addition, the designer of the circuit board 100 would also prefer that the integrated circuit chip vendors perform functional testing on the integrated circuit chips. Specifically, the designer of the circuit board 100 would like the integrated circuit chip vendor to verify that the integrated circuit chips they produce function in the manner in which they have been modeled. This is a difficult task and one which is placed upon production test. The production test engineer is required to handcraft various tests to attempt to test the functionality of the integrated circuit chips. The difficulty is that the production test engineer is unable to fully test the complete functionality of the integrated circuit chips using handcrafted tests. The functioning of the integrated circuits is simply too complex for a human to handcraft a sufficient number of tests in a reasonable amount of time so that the integrated circuit chip can be functionally verified for the design for which it is intended.
Designers are responsible for creating the designs of chips and verifying that all important design criteria have been met. The production test engineers are responsible for ensuring high quality and reliability of the chips. Often, a production test engineer ends up trying to make design verification tests (designed by the designer) succeed on automatic testing equipment (ATE) systems. However, the differences between the simulation world of the designer (which is software modeling) and the physical world of the production test engineer (ATE systems) make it difficult to translate simulation tests to ATE tests in a straightforward manner. The designer uses a software model which is an approximation of a real circuit. Judgment is used to filter responses for aberrations that are attributes of the modeling process rather than true characteristics of the circuit. As a result, the process of design verification is a highly creative, judgment-driven, human and imperfect process. The production test engineer tests the physical realization of the circuit (chip) on an ATE system. The ATE system performs physical experiments on the chip and physical laws and constraints are involved with such real world testing. These physical laws and constraints dictate limits that may not have been observed during design verification. As a result of these differences, it becomes very difficult to directly translate simulation data (from the design verification) to tester data (for an ATE system). What happens often is that the design verification test is shortened, relaxed, and then augmented to address considerations that are important to ATE systems. The process of transforming a verification test to a useful production test is generally difficult for someone not familiar with both the design and the ATE system. Hence, there is a need for an automatic way of efficiently and accurately transforming simulation data from the software world to tester data in the physical world with minimal involvement of the designer.
Broadly speaking, the invention relates to techniques for functionally testing integrated circuit chips for the particular design for which they are intended. The invention intelligently transforms a test designed for verifying the design of a simulation model of an electronic system to data for an isolated test of a particular integrated circuit within the simulation model on an integrated circuit (IC) tester.
The invention can be implemented in numerous ways, including as a method, an apparatus, or a system, or on a computer readable medium.
A first implementation of the invention pertains to a computer-implemented method for functionally testing an integrated circuit chip using test patterns derived from simulation tests performed on a system model which includes the integrated circuit chip. The method includes the following operations: receiving a simulation model for an electronic system and a simulation test for the simulation model; identifying a portion of the simulation model to be individually tested; producing portion-specific simulation test data based on at least the portion identified and the simulation test; and deriving test patterns and timing information for testing the portion identified using the portion-specific simulation test data. Preferably, the portion identified is an integrated circuit chip, and the derived test patterns and timing information are IC tester data used on an automatic testing equipment (ATE) type chip tester. Additionally, the method may also determine, using the simulation model, internal control signals for bidirectional pins or tristate output pins within the portion of the simulation model, and include one or more dead cycles within the derived test patterns so that the bidirectional pins can be properly tested.
A second implementation of the invention pertains to an automated method for producing test patterns for testing an IC chip on an IC tester. The test patterns are derived from a system model and a simulation test for the system model. The method includes the following operations: receiving the system model; determining the signals within the system model that correspond to pins of the IC chip; determining internal control signals for the pins of the IC chip that are bidirectional or tristate outputs; using a simulation tool, the system model and the signals determined by the previous operations, produce a time event list for the IC chip, the time event list includes signal values and relative times for signal changes; scanning the time event list to determine a tester cycle for the IC tester and a number of frames for the tester cycle; and deriving test patterns and timing information for testing the IC chip on the IC tester in accordance with the time event list.
A third implementation of the invention pertains to a computer-implemented method for functionally testing an integrated circuit chip using test patterns derived from simulation tests performed on a system model which includes the integrated circuit chip. The method includes the following operations: receiving simulation test information for testing the system model; extracting signals pertaining to the integrated circuit chip from the simulation test information; and deriving test patterns and timing information for testing the integrated circuit chip based on the extracted signals. The method may then test the functionality of the integrated circuit chip on an IC tester using the derived test patterns and the timing information. The invention may also determine, using the simulation test information, internal control signals for bidirectional pins within the portion of the electronic system, and the deriving operates to include one or more dead cycles within the derived test patterns so that certain of the bidirectional pins can be properly simulation.
A fourth implementation of the invention pertains to an apparatus for functionally testing an integrated circuit chip using test patterns derived from simulation tests performed on a system model which includes the integrated circuit chip. The apparatus includes at least the following: means for receiving a simulation model for an electronic system and a simulation test for the simulation model; means for identifying a portion of the simulation model to be individually tested; means for producing portion-specific simulation test data based on at least the portion identified and the simulation test; and means for deriving test patterns for testing the portion identified using the portion-specific simulation test data.
A fifth implementation of the invention pertains to an automated simulation-to-test pattern conversion system for use in testing an integrated circuit chip. The apparatus includes at least a signal extractor for receiving data associated with an electronic system simulation model, and for identifying signals within the electronic system simulation model that are relevant to testing the integrated circuit chip and for identifying control signals for bidirectional pins or tristate output pins within the electronic system simulation model; a test information producing unit for producing chip-specific test information for the integrated circuit chip to be tested in accordance with the electronic system simulation model, the identified signals, and a simulation test for the electronic system simulation model; and a test pattern processor for receiving the chip-specific test information and the identified control signals and for producing test patterns for testing the integrated circuit chip functionally as it was tested on a system level. Preferably, the test patterns produced by the test pattern processor are for an IC tester, and the test pattern processor (i) determines a number of frames for a tester cycle for the IC tester, (ii) determines from the chip-specific test information and the identified control signals, the bidirectional pins of the integrated circuit chip that require dead cycles, (iii) provides a dead cycle within the test patterns for the bidirectional pins of the integrated circuit chip that are determined to change direction in the same tester cycle of the chip-specific test information; and (iv) determines timing or sequencing information for driving or strobing pins of the integrated circuit chip during the tester cycle.
A sixth implementation of the invention pertains to a computer readable medium containing program instructions for functionally testing an integrated circuit chip using test patterns derived from simulation tests performed on a system model which includes the integrated circuit chip. The computer readable medium includes computer readable code devices for receiving a simulation model for an electronic system and a simulation test for the simulation model; computer readable code devices for identifying a portion of the simulation model to be individually tested; computer readable code devices for producing portion-specific simulation test data based on at least the portion identified and the simulation test; and computer readable code devices for deriving test patterns and timing information for testing the portion identified using the portion-specific simulation test data.
The invention provides advantages over previous techniques for functionally testing integrated circuit chips. One advantage of the invention is that the integrated circuit chips can be tested more thoroughly and cost effectively. In particular, design verification tests created during chip design can be automatically converted for testing fabricated chips on an IC tester. Fault coverage is not sacrificed and the test patterns can be automatically produced for an ATE tester in accordance with the specifications of the ATE tester. Hence, the designer need not be concerned with ATE considerations or ATE specifications when designing design verification tests. Another advantage of the invention is that the testing of the integrated circuit chip is customized for the design for which the chip is intended. Another advantage of the invention is that accurate fault simulation and fault grading of the patterns are facilitated.
Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principals of the invention.